Conference Agenda

Chipless RFID tags can be integrated into electronic circuit carriers as easily and cost-effectively as barcodes, DMC or data matrix codes. The eponymous chiplessness not only avoids assembly work and component costs, but also makes the marking of the assembly available very early on in the manufacturing process. The concept presented here operates at microwave frequencies and is realised in LTCC multilayer technology. The ceramic substrate further extends the operating temperature range. Reading the tag in the near field reduces ambiguities and interference in practical use. In the presented concept, the information is encoded in the frequency domain, where the presence or absence of a null at a distinct frequency corresponds to a binary digit. By employing a wideband dual polarized antenna, the impinging RF signal is received by the tag, processed by a set of resonators used to encode the bits, and finally retransmitted with a 90° polarization rotation. For improving the sensitivity and precision of the code reading, a reference structure can be efficiently applied. The paper presents the concept and realization of the tag, including an analysis and comparison between the numerical and measured results.

OPMMEG project (funded by European Innovation Council, ID 101099379) is aiming to develop the technological elements of optically-pumped magnetometers (OPM) to be utilized in magnetoencephalography (MEG), which is a non-invasive imaging technique for investing human brain functions. MEG operates by detecting magnetic fields naturally produced by the brain, with no applied fields or injections. Typical applications are epilepsy and mild traumatic brain injuries.

OPMs are a cryogen-free quantum sensor technology with extraordinary magnetic sensitivity. In comparison with the currently used SQUID-based MEGs, OPM provides a superior balance of sensitivity, size and proximity to the cortex, but have not yet been implemented in technologies that are simultaneously manufacturable at scale, high-performing, and cost-effective. In this project an OPM array will be developed to meet these requirements for wide-spread use of OPMs in MEG.

The sensor array needs a high-power VCSEL and high-quality miniaturised sensor package. As a final outcome, a helmet with OPM sensors placed close to each other will be demonstrated. The project brings together world leaders in quantum sensor components and systems, commercial MEG systems and MEG applications. OMPMEG will build a value chain from photonic devices to systems connecting all relevant stakeholders. An essential part of this EIC-funded project is to study commercialization aspects of OPMs in MEG and also other applications. The conference presentation will show the status after the 1^st project year.

This paper describes the design of a silicon nanowire-based sensor chip and the optimization of various parameters and recipes, such as photolithography and e-beam deposition. We describe packaging issues with nanometer-thickness metal deposition. The electrical response of the silicon nanowire integrated sensor array was studied by electrical current (IV) analysis. The sensors are designed to detect chemicals and biomolecules, potentially acting as a novel biosensor for biomedical diagnosis in the future.

In space sector, the growing trend towards in digitalization and the demand of ever more compact and integrated devices have led to an ever-increasing interest in SiP Technology that is identified as a key technology for future space equipment. SiP offers the advantage of integrating different functions based on heterogeneous technologies on the same substrate. For instance, SiP technology enables the integration of different functions utilizing various semiconductor processes, allowing for flexibility in combining components such as ADC/DAC with digital routing and processing. This approach also facilitates the reusability of existing intellectual property (IP), resulting in time and cost savings compared to the development of a dedicated System-on-Chip (SoC). Furthermore, SiP technology helps to decrease the power consumption over capacity ratio and increase the compactness of the unit. It offers the ability to enhance capacity while minimizing the size and volume of the function.

In the frame of FOCUSING, a synergic Horizon Europe project between, IMT, Panasonic, Somacis, Thales Alenia Space France, Thales Alenia Space Italy and Hytek, the main objective is to develop innovative SiP building blocks in Europe using state-of-the-art base materials, advanced packaging techniques, and final integration on motherboard. Different systems are being developed and assessed to cover a wide range of applications, including:

• Power supply SiP using embedding technology
• High speed data rate SiP, using complex build-up structure
• High frequency mix RF/ Digital SiP using as well complex build-up structure.

This paper specifically focuses on the development of the high-speed data rate SiP, addressing the architecture tradeoff and chip selection for the SiP demonstrator capable of handling data rates up to 25 GHz

Advanced substrates necessitate a high I/O count to represent complex ASIC dies with up to 10,000 bumps, each with a pitch of 200µm or less. The substrate is characterized by employing complex materials compatible with extremely low dielectric thickness and thin base copper. A substantial number of micro-vias are required to interconnect all dies on a 45x45mm substrate.

A focus will be done on the architecture design of the substrate. The 6+n+6 build-up shall be compatible of the complex dies fan-out exhibiting fine tracks and spaces (25/25µm) and be as much as reliable for space environment constrains. To do so, different stacking architectures have been developed on the same substrate. Initial signal integrity simulations have been done to determine the best electrical architecture (stacked or staggered) to implement. On the other hand, with the benefit of daisy-chain dies, will provide the possibility of testing each structures definition implemented on the test vehicle to highlight the best reliable and functional configuration.

Given that the validation of such a complex substrate is not covered by existing space standards, this paper discusses also the definition of an adapted test flow approach based on space standards. This approach aims to rely on a known test definition but tailored with adapted tests for this technology. The results will be presented as far as they are available.