Session | ||
DTM4_Device Level Modeling
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Presentations | ||
11:00am - 11:25am
Latency Insertion Method for FinFET Simulation Incorporating Parasitic Source/Drain Resistances University of Illinois at Urbana Champaign, Urbana, USA 11:25am - 11:50am
CANCELLED: Adaptive Artificial Neural Networks for Power Loss Prediction in SiC MOSFETs 1Sanan Semiconductor, Munich, Germany; 2Sanan Semiconductor, Changsha, China 11:50am - 12:15pm
Simulation Analysis on Thermal Performance of Lidless Fan-out Package 1School of Integrated Circuits, Tsinghua University, Beijing, China, Peoples Republic of; 2Beijing National Research Center for Information Science and Technology, Beijing, China, Peoples Republic of |