Conference Agenda

Session
DTM4_Device Level Modeling
Time:
Thursday, 12/Sept/2024:
11:00am - 12:15pm

Session Chair: Przemyslaw Gromala, Robert Bosch GmbH
Location: MOA 3

MOA 3

Presentations
11:00am - 11:25am

Latency Insertion Method for FinFET Simulation Incorporating Parasitic Source/Drain Resistances

Yi Zhou, Jose E. Schutt-Aine

University of Illinois at Urbana Champaign, Urbana, USA



11:25am - 11:50am

CANCELLED: Adaptive Artificial Neural Networks for Power Loss Prediction in SiC MOSFETs

Giovanni Di Nuzzo1, Ajay Poonjal Pai1, YiChe Su2

1Sanan Semiconductor, Munich, Germany; 2Sanan Semiconductor, Changsha, China



11:50am - 12:15pm

Simulation Analysis on Thermal Performance of Lidless Fan-out Package

Yongbo Wu1, Jian Cai1,2, Changming Song1, Lin Tan1, Qian Wang1,2

1School of Integrated Circuits, Tsinghua University, Beijing, China, Peoples Republic of; 2Beijing National Research Center for Information Science and Technology, Beijing, China, Peoples Republic of