Session | ||
DTM1_Co-design and Modeling for Chiplets
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Presentations | ||
2:40pm - 3:05pm
Simulations of Wafer-to-wafer Bonding Dynamics and Deformation Mechanisms imec, Loewen, Belgium 3:05pm - 3:30pm
Signal Integrity Optimization for CoWoS Chiplet Interconnection Design Assisted by Reinforcement Learning 1Institute of Microelectronics (IME), Singapore, Republic of Singapore; 2School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Republic of Singapore 3:30pm - 3:55pm
Finite Element Analysis of Stress Variation of Hybrid Bonding During Miniaturization of Interconnects 1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China, People's Republic of; 2School of Integrated Circuits, Peking University, Beijing, China, People's Republic of; 3Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China, People's Republic of; 4National Key Lab of Micro/Nano Fabrication Technology, China, People's Republic of |