IEEE ESTC 2024
September 11–13, 2024 | Berlin, Germany
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview | |
Location: MOA 5 MOA 5 |
Date: Wednesday, 11/Sept/2024 | |
8:30am - 10:30am |
PDC: “Advanced Packaging for MEMS and Sensors” I Location: MOA 5 Course instructor: Horst Theuss |
10:45am - 12:45pm |
PDC: “Advanced Packaging for MEMS and Sensors” II Location: MOA 5 Course instructor: Horst Theuss |
2:40pm - 3:55pm |
AP1_Advanced Substrates Location: MOA 5 Chair: Andreas Ostmann, IZM Development of Packaging Technology for 2.xD Advanced Packages; Fine Bump Interconnection, Fine Cu Wiring and Large Package 3:05pm - 3:30pm Advancing Chiplet Architecture Through Heterogeneous Integration on Laser-processed Glass Substrates 3:30pm - 3:55pm High Rate and Selective (Deep) Reactive-ion Etching Process for the Formation of High-density Vertical Interconnects into Dielectric Build-up Films |
5:00pm - 6:15pm |
AP2_Hybrid Bonding I Location: MOA 5 Chair: E Jan Vardaman, TechSearch International, Inc. Ultra Low Temperature Hybrid Bonding: Morphological and Electrical Characterizations 5:25pm - 5:50pm Overlay Scaling Error Reduction for Hybrid Die-To-wafer Bonding 5:50pm - 6:15pm Scatterometry Application on Cu/SiCN Surface Topography Towards High Volume Manufacturing |
Date: Thursday, 12/Sept/2024 | |
9:15am - 10:30am |
AP3_Hybrid Bonding II Location: MOA 5 Chair: Rolf Aschenbrenner, Fraunhofer IZM High Precision Direct Transfer Bonding for Submicron Die-to-wafer in 3D/Heterogeneous Integration 9:40am - 10:05am Bond Strength Measurement for Wafer-level and Chip-level Hybrid Bonding 10:05am - 10:30am Optimization of Cu/SiCN Hybrid Bonding Process Using a Cohesive Zone Model |
11:00am - 12:15pm |
AP4_Advances in WLP Technologies I Location: MOA 5 Chair: Rolf Aschenbrenner, Fraunhofer IZM Semi-Additive Fine Pitch RDL Litho-Process Development of 1000nm CD Using low-NA 300mm i-line Stepper 11:25am - 11:50am Study of Cross-contamination in Multi-chamber PVD Systems used for High-throughput Seed Layer Deposition 11:50am - 12:15pm Enhanced Defect Detection with Deep Neural Networks Post Wafer Bonding |
1:45pm - 3:15pm |
AP5_Advances in WLP Technologies II Location: MOA 5 Chair: Michael Schiffer, Fraunhofer IZM Package Assembly Design Kits (PADK’s) – The Future of Advanced Wafer-level Manufacturing 2:10pm - 2:35pm Fan-out Packaging Reaching New Heights: Market and Technology Overview 2:35pm - 3:00pm Optimizing Laser Direct Write for Fan Out Packaging |
3:45pm - 5:15pm |
AP6_Challenges and Solutions for HI Location: MOA 5 Chair: Kay Essig, ASE Group Acoustic MEMS Packaging for Audio Micro-System Applications 4:10pm - 4:35pm IMC Assisted Die-bonding for Stacked Device Integration 4:35pm - 5:00pm High-throughput In-line SEM Metrology for Cu Pad Nanotopography for Hybrid Bonding Applications |
Date: Friday, 13/Sept/2024 | |
9:15am - 10:30am |
AP7_Fan Out Packages Location: MOA 5 Chair: Erik Jung, Fraunhofer IZM INVITED TALK: Accelerating the AI Economy through Heterogeneous Integration 9:40am - 10:05am Development of an Adaptive Re-distribution Patterning Process for Fan-out Packages with Embedded High I/O Components 10:05am - 10:30am On the Design and Fabrication of SMT-compatible 3D-Freeform Antennas Based on Compression Molding and Direct Cu-Metallization |
11:00am - 12:15pm |
AP8_Fan Out Reliability Aspects Location: MOA 5 Chair: Grace O'Malley, INEMI Power Delivery for AI/HPC Microprocessors 11:25am - 11:50am Reliability and RF Performance Assessment of Heterogeneous Integrated FO-WLP Test Structure Packages for Mixed RF Digital Front-End Application 11:50am - 12:15pm No Warpage and Fast Cure: UV-molding for FOWLP/FOPLP |
1:45pm - 3:00pm |
AP9_Power Electronics Packaging Location: MOA 5 Chair: Klaus Pressel, Infineon Additive Fan-out Panel-level Processing for Power MOSFET Devices 2:10pm - 2:35pm Advancing Packaging Solutions: Integrating Power Electronics Using LTCC Technology 2:35pm - 3:00pm Thermal Diffusivity Investigation of a Heat Pipe |
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