IEEE ESTC 2024
September 11–13, 2024 | Berlin, Germany
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Session Overview |
Date: Wednesday, 11/Sept/2024 | |||||
8:00am - 2:30pm |
Registration |
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8:30am - 10:30am |
„IEEE EPS Heterogeneous Integration Roadmap“ (HIR) I Location: MOA 10-12 |
PDC: “Advanced Packaging for MEMS and Sensors” I Location: MOA 5 Course instructor: Horst Theuss
more Info
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PDC: “Automotive Electronics Reliability – Assurance Approaches and Challenges” I Location: MOA 4 Course instructor: Pradeep Lall
more Info |
PDC: “Flip Chip Fabrication and Applications“ I Location: MOA 3 Course instructor: Eric Perfecto
more Info |
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10:30am - 10:45am |
Break |
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10:45am - 12:45pm |
„IEEE EPS Heterogeneous Integration Roadmap“ (HIR) II Location: MOA 10-12 |
PDC: “Advanced Packaging for MEMS and Sensors” II Location: MOA 5 Course instructor: Horst Theuss
more Info |
PDC: “Automotive Electronics Reliability – Assurance Approaches and Challenges” II Location: MOA 4 Course instructor: Pradeep Lall
more Info |
PDC: “Flip Chip Fabrication and Applications“ II Location: MOA 3 Course instructor: Eric Perfecto
more Info |
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11:00am - 3:00pm |
Exhibition Setup Location: Atrium |
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12:45pm - 1:30pm |
Break |
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1:30pm - 1:45pm |
Opening Location: MOA 10-12 Opening remarks Tanja Braun General Chair IEEE ESTC2024 Welcome on behalf of the German Ministry for Education and Research (BMBF) Engelbert Beyer Deputy Director-General of Directorate 51, Technology-Oriented Research for Innovation, BMBF, Germany |
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1:45pm - 2:30pm |
Keynote 1 Location: MOA 10-12 "A Vision for Modular, Ubiquitous and Scalable Compute Systems" Bernd Waidhas Principal Engineer, Silicon Packaging Architecture, Intel |
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2:30pm - 2:40pm |
Room change |
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2:40pm - 3:55pm |
MIP1_Advanced Material Architectures for Interconnects Location: MOA 10-12 Chair: Glenn Hamilton Ross, Aalto University Solid-state Growth Kinetics of Compound Layers in Electroplated Cu-In Layer Systems 3:05pm - 3:30pm Superconducting Superlattice Interconnects for Cryogenic Systems 3:30pm - 3:55pm Aluminium-Aluminium Wafer Level Thermo Compression Bonding Using Thick Electroplated Aluminium Bonding Frames |
AP1_Advanced Substrates Location: MOA 5 Chair: Andreas Ostmann, IZM Development of Packaging Technology for 2.xD Advanced Packages; Fine Bump Interconnection, Fine Cu Wiring and Large Package 3:05pm - 3:30pm Advancing Chiplet Architecture Through Heterogeneous Integration on Laser-processed Glass Substrates 3:30pm - 3:55pm High Rate and Selective (Deep) Reactive-ion Etching Process for the Formation of High-density Vertical Interconnects into Dielectric Build-up Films |
Opto1_Photonic Module Packaging Location: MOA 4 Chair: Henning Schröder, Fraunhofer IZM Array Packaging with Integrated Mirrors for High Power Multi-chip UVC-LED Modules 3:05pm - 3:30pm Modular Integration of Quantum Cascade Lasers and Drivers in Glass Bench 3:30pm - 3:55pm Improving the Thermal Management of Power LED Arrays with Diamonds |
DTM1_Co-design and Modeling for Chiplets Location: MOA 3 Chair: Chris Bailey, Arizona State University Simulations of Wafer-to-wafer Bonding Dynamics and Deformation Mechanisms 3:05pm - 3:30pm Signal Integrity Optimization for CoWoS Chiplet Interconnection Design Assisted by Reinforcement Learning 3:30pm - 3:55pm Finite Element Analysis of Stress Variation of Hybrid Bonding During Miniaturization of Interconnects |
Power1_Electronics Measurement and Simulation Location: MOA 1+2 Chair: Aurelian Kotlar, Eberspächer Dynamic Calibration of Junction Temperature of SiC MOSFETs for Power Cycling 3:05pm - 3:30pm Contact Thermography – New Findings, New Ideas 3:30pm - 3:55pm Abrasion Characterization of Graphene-enhanced Thermal Interface Materials for Electronics Thermal Management Applications |
3:00pm - 8:00pm |
Exhibition Location: Atrium |
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3:55pm - 4:25pm |
Coffee Break & Exhibition Location: Atrium |
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3:55pm - 5:00pm |
Poster Session 1 Location: Atrium Chair: Karl-Friedrich Becker, Fraunhofer IZM Fabrication of Fine-Pitch Cu-Sn Microbumps Using Electroplating and Wet Seed Layer Etching Eclipse Versus Conventional Optical Choppers: Modeling and Analysis Development of HTC Tests on Module Basis Low-temperature Adhesive Wafer Bonding for Film Layer Transfer Adhesive Solutions for Closed Cavity Packaging Infrared Optical Solutions for Void Inspection of Bonded Wafers and Bonding Overlay Control Investigation of RF Characteristics of Chiplet to PCB Transitions for Advanced HPC Packaging Solutions Molding Process Simulation and Viscoelastic Model for Package Warpage Anticipation 2.5D/3D Chiplets Approach to Advanced Packaging Solutions Automatized Multi-objective Optimization for Reliability of Power Electronics Adhesion Layer Analysis by Spectroscopic Ellipsometry Inline Oxide Removal Through Openair-plasma to Solve Delamination and Improve Bonding in Electronics Heat Spreading in Uncovered Copper Sintered Die-Attach Layers Examined with Lock-In Thermography Evaluation of Mobile Data Center Cooling Performance Based on Embedded Cooling |
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4:25pm - 4:55pm |
Exhibitor Pitches Location: MOA 10-12 |
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4:55pm - 5:00pm |
Room change |
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5:00pm - 6:15pm |
MIP2_Advanced Interconnection Metallurgical Materials and Interconnects Location: MOA 10-12 Chair: Ali Roshanghias, Silicon Austria Labs GmbH Tuning of Copper Grain Size for Integration in Hybrid Bonding Applications 5:25pm - 5:50pm Fine Pitch Aluminum Hybrid Bonding at Wafer Level: Overcoming the Challenges in Plating, Passivation and Planarization 5:50pm - 6:15pm Surface Activated Bonding for Hybrid and All-metal 3D (AM3D) Interconnect |
AP2_Hybrid Bonding I Location: MOA 5 Chair: E Jan Vardaman, TechSearch International, Inc. Ultra Low Temperature Hybrid Bonding: Morphological and Electrical Characterizations 5:25pm - 5:50pm Overlay Scaling Error Reduction for Hybrid Die-To-wafer Bonding 5:50pm - 6:15pm Scatterometry Application on Cu/SiCN Surface Topography Towards High Volume Manufacturing |
Opto2_Heterogenous PIC Integration Location: MOA 4 Chair: Giovanni Delrosso, VTT Laser-Assisted Bonding of a Miniature Multichannel Laser Diode Chip to a Silicon Photonics Integrated Circuit with Through-Silicon Alignment 5:25pm - 5:50pm Over 100-GHz Bridge Chip Interconnection Between Photonic and Electrical ICs with a Heat-insulating Stress-relief Membrane Structure 5:50pm - 6:15pm Advanced Ultrathin Spray Coating Process Technology for Heterogeneous Integration Applications |
DTM2_Reduced Order Modeling for Advanced Packaging Location: MOA 3 Chair: Kshitij Anil Kolas, Fraunhofer ENAS Reduced-Order Modelling for Coupled Thermal-Mechanical Analysis and Reliability Assessments of Power Electronic Modules with Nonlinear Material Behaviours 5:25pm - 5:50pm Highly Efficient Modeling of Solder Balls and Their Visco-plastic Behavior Applying the Energy Conserving Sampling and Weighting Method 5:50pm - 6:15pm Coupled Electrothermal Analysis with Reduced Order Models for Optimizing GaN HEMTs Performance in Traction Inverters |
Power2_Power Semiconductor Packaging and Cooling Location: MOA 1+2 Chair: Gudrun Feix, ECPE European Center for Power Electronics Model-based Development to Improve Electrical and Thermal Performances for Robust Si Power MOSFETs Using Embedded Die Packaging Technology 5:25pm - 5:50pm Research on Ultra-compact 3D SiC Power Module for EVs with Double Layer Cooling Technology 5:50pm - 6:15pm An Introduction to Wire-bondless Discrete GaN Power Packages with Top-Side Cu Sinterconnects® |
6:15pm - 8:00pm |
Welcome Reception Location: Atrium |
Contact and Legal Notice · Contact Address: Privacy Statement · Conference: IEEE ESTC 2024 |
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